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Author Howland, C. ♦ Blanksby, A.
Sponsorship IEEE Solid State Circuits Soc.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2001
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Parity check codes ♦ Turbo codes ♦ Iterative algorithms ♦ Iterative decoding ♦ Sparse matrices ♦ Throughput ♦ Power dissipation ♦ Message passing ♦ Bipartite graph ♦ Very large scale integration
Abstract A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm translates into extremely low switching activity with power dissipation under 220 mW.
Description Author affiliation: VLSI Res. Dept., Agere Syst., Holmdel, NJ, USA (Howland, C.)
ISBN 0780365917
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2001-05-09
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 381.79 kB
Page Count 4
Starting Page 293
Ending Page 296


Source: IEEE Xplore Digital Library