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Author Joon-Sung Yang ♦ Touba, N.A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Flip-flops ♦ Observability ♦ Clocks ♦ Monitoring ♦ Silicon ♦ Logic gates ♦ Compaction ♦ MISR ♦ Silicon debug ♦ Scan-based debug ♦ Periodic monitoring
Abstract Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is time consuming as many scan dumps may be required. In this paper, conventional scan chains that have non-destructive scan out capability are configured to operate as multiple MISRs during system operation. Information from the multiple MISRs is monitored periodically to identify erroneous behavior. A procedure for constructing the MISRs to maximize debug capability is described. A three step process is used to zero in on the first clock cycle in which an error is present with a small number of scan dumps. Moreover, a method for bypassing errors is described to permit debug in the presence of multiple bugs.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX (Joon-Sung Yang; Touba, N.A.)
ISBN 9780769533650
ISSN 15505774
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-10-01
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 392.67 kB
Page Count 9
Starting Page 125
Ending Page 133


Source: IEEE Xplore Digital Library