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Author Li-Ming Denq ♦ Cheng-Wen Wu
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Built-in self-test ♦ Routing ♦ Circuit testing ♦ Communication system control ♦ Random access memory ♦ Automatic testing ♦ Logic testing ♦ Centralized control ♦ Fault diagnosis ♦ Change detection algorithms
Abstract It is common that an SOC contains hundreds or even thousands of heterogeneous embedded memories. Many of these embedded memories have wide data words, leading to high routing penalty from the BIST circuits. Previous BIST schemes solve the problem using serial interface, e.g., based on the IEEE 1500 architecture and novel scan approaches, to reduce the routing area overhead. However, serial approaches do not allow at-speed test and diagnosis, and are very slow. In this paper, we propose a hybrid BIST architecture that reduces the routing penalty, while allowing at-speed test and diagnosis of the memory cores. The test time is close to that of a typical parallel BIST method. Experimental results show that the proposed BIST can effectively reduce the area overhead.
Description Author affiliation: Nat. Tsing Hua Univ., Hsinchu (Li-Ming Denq; Cheng-Wen Wu)
ISBN 9780769528908
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-10-08
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 203.12 kB
Page Count 6
Starting Page 349
Ending Page 354

Source: IEEE Xplore Digital Library