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Author Higami, Y. ♦ Takahashi, H. ♦ Kobayashi, S. ♦ Saluja, K.K.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2011
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit faults ♦ Clocks ♦ Delay ♦ Logic gates ♦ Vectors ♦ Automatic test pattern generation ♦ Integrated circuit modeling ♦ launch-on-capture test ♦ test generation ♦ clock delay fault ♦ transition fault
Abstract Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods.
ISBN 9781457719844
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-11-20
Publisher Place India
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 310.72 kB
Page Count 6
Starting Page 1
Ending Page 6


Source: IEEE Xplore Digital Library