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Author Fisher, A.L. ♦ Highnam, P.T. ♦ Rockoff, T.E.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1989
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Abstract A four-processor chip, for use in processor arrays for image computations, is described. The full-custom 2-μm CMOS chip contains 56669 transistors and runs instructions at 10 MHz. 512 16-bit processors and external memory fit on two industry standard cards to yield 5-GIPS (billions of instructions/s) peak throughput
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1989-05-15
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 560.00 kB


Source: IEEE Xplore Digital Library