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Author Chin-Cheng Kuo ♦ Wei-Yi Hu ♦ Yi-Hung Chen ♦ Jui-Feng Kuan ♦ Yi-Kan Cheng
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2012
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Analytical models ♦ Integrated circuit modeling ♦ Yield estimation ♦ Accuracy ♦ Phase locked loops ♦ Monte Carlo methods ♦ Algorithm design and analysis ♦ trimmed-sample ♦ Monte Carlo simulation ♦ analog circuits ♦ yield-aware design flow
Abstract This paper proposes efficient trimmed-sample Monte Carlo (TSMC) methodology and novel yield-aware design flow for analog circuits. This approach focuses on “trimming simulation samples” to speedup MC analysis. The best possible yield and the worst performance are provided “before” MC simulations such that designers can stop MC analysis and start improving circuits earlier. Moreover, this work can combine with variance reduction techniques or low discrepancy sequences to reduce the MC simulation cost further. Using Latin Hypercube Sampling as an example, this approach gives 29× to 54× speedup over traditional MC analysis and the yield estimation errors are all smaller than 1%. For analog system designs, the proposed flow is still efficient for high-level MC analysis, as demonstrated by a PLL system.
Description Author affiliation: Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan (Chin-Cheng Kuo; Wei-Yi Hu; Yi-Hung Chen; Jui-Feng Kuan; Yi-Kan Cheng)
ISBN 9781450311991
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2012-06-03
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
e-ISBN 9781450311991
Size (in Bytes) 1.09 MB
Page Count 6
Starting Page 1113
Ending Page 1118


Source: IEEE Xplore Digital Library