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Author Hsieh, D. ♦ Feipei Lai
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1993
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Testing ♦ Memory management ♦ Mars ♦ Multiprocessing systems ♦ Pins ♦ Multiprocessor interconnection networks ♦ Central Processing Unit ♦ Access protocols ♦ Hardware
Abstract A design and test of memory management unit and cache controller (MMU/CC) chip for the Multiprocessor Architecture Reconciling Symbolic with numerical processing (MARS) are presented in this paper. MMU/CC can provide the memory access requirement of the MARS system for one load per cycle in the absence of cache miss, TLB miss, exception or interrupt. Not only the cache and memory operations are supported, but also an invalidation cache coherence protocol is embedded. The MMU/CC chip has 66290 transistors and 144 pins. The die size is 8653 /spl mu/m * 7114 /spl mu/m. We take a detailed look at critical issues of the design trade-offs, floor-planning, and testing.
Description Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Hsieh, D.; Feipei Lai)
ISBN 0780312333
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1993-10-19
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 328.12 kB
Page Count 4
Starting Page 10
Ending Page 13


Source: IEEE Xplore Digital Library