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Author Vintan, L. ♦ Steven, G.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1997
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Process design ♦ Delay ♦ Out of order ♦ Processor scheduling ♦ Vehicles ♦ Runtime ♦ Reduced instruction set computing ♦ Pipelines
Abstract Most research on multiple instruction issue processor architecture assumes a perfect memory hierarchy and concentrates on increasing the instruction issue rate of the processor. In contrast, the paper assumes an ideal processor model and seeks to quantify the limitations placed on superscalar processor performance by the memory hierarchy. The paper concludes that sustaining processor issue rates of four or more will probably ultimately require systematic preloading of cache blocks and the use of trace caches.
Description Author affiliation: Sibiu Univ., Romania (Vintan, L.)
ISBN 0818682159
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-09-01
Publisher Place Hungary
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 433.94 kB
Page Count 6
Starting Page 252
Ending Page 257


Source: IEEE Xplore Digital Library