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Author Singh, U. ♦ Chen, C.Y.R.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1990
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Equations ♦ Algorithm design and analysis ♦ Delay ♦ Matrix converters ♦ Logic circuits ♦ Automatic control ♦ Logic design ♦ Sun ♦ Merging ♦ Terminology
Abstract An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of O(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area.<<ETX>>
Description Author affiliation: Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA (Singh, U.; Chen, C.Y.R.)
ISBN 0897913639
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1990-06-24
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 641.72 kB
Page Count 6
Starting Page 462
Ending Page 467


Source: IEEE Xplore Digital Library