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Author Shaolei Quan ♦ Qiang Qiang ♦ Chin-Long Wey
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Operational amplifiers ♦ Stress ♦ Circuit testing ♦ Circuit simulation ♦ Logic testing ♦ CMOS technology ♦ Voltage ♦ Integrated circuit testing ♦ Switching circuits ♦ Switches
Abstract Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.
Description Author affiliation: Michigan State University, US (Shaolei Quan)
ISBN 0769524818
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-12-18
Publisher Place India
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 281.79 kB
Page Count 6
Starting Page 70
Ending Page 75


Source: IEEE Xplore Digital Library