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Author Roy, S. ♦ Arts, H. ♦ Banerjee, P.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1998
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Cost function ♦ Capacitance ♦ Energy consumption ♦ Design optimization ♦ Contracts ♦ Binary trees ♦ Art ♦ Concurrent computing ♦ Circuit synthesis ♦ Digital circuits
Abstract This paper describes algebraic techniques that target low power consumption. A unique power cost function based on decomposed factored form representation of a Boolean expression is introduced to guide the structural transformations. Circuits synthesized by the SIS and POSE consume 54.5% and 10.4% more power than that obtained by our tool respectively.
Description Author affiliation: Ambit Design Syst., Santa Clara, CA, USA (Roy, S.)
ISBN 0818683597
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1998-02-23
Publisher Place France
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 47.54 kB
Page Count 2
Starting Page 967
Ending Page 968


Source: IEEE Xplore Digital Library