Access Restriction

Author Lewis, W.J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1989
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Automatic testing ♦ Circuit testing ♦ Logic testing ♦ Test pattern generators ♦ Registers ♦ Latches ♦ Feedback ♦ Costs ♦ Circuit faults ♦ Pattern analysis
Abstract The problem of determining the number of cycles of test-pattern generation required to exhaustively test a block of logic is investigated, considering the case where the generator has more stages than the logic has inputs. Some statistical results are presented, and these are then compared with simulation results. The results show that it is easily possible to simulate the configurations used in current circuit designs. The results produced are exact and the cycle counts are typically 50% of those suggested by the statistical approach (for 0.999 probability of exhaustive testing). An example from a real chip which had a 14-bit generator feeding 56 testable units took only 48 s of CPU time to simulate.<<ETX>>
Description Author affiliation: Plessey Res. & Technol. Ltd., Towcester, UK (Lewis, W.J.)
ISBN 0818619376
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1989-04-12
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 263.12 kB
Page Count 6
Starting Page 403
Ending Page 408

Source: IEEE Xplore Digital Library