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Author Hougardy, S. ♦ Nieberg, T. ♦ Schneider, J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2013
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Field effect transistors ♦ Routing ♦ Logic gates ♦ Layout ♦ Steiner trees ♦ Algorithm design and analysis
Abstract In this paper we present BonnCell, our solution to compute leaf cell layouts in VLSI design. Our placement algorithm allows to find very compact solutions and uses an accurate target function to guarantee routability. The routing algorithm handles all nets simultaneously using a constraint generation MIP based approach. Finally, yield and electromigration properties are improved in a post-processing phase. Our approach considers design rules already during placement and routing, is able to treat gridless technologies, and easily adapts to new design rules and future technologies as for example double patterning in 14nm and beyond. The experimental results on current 22nm designs of our industry partner show significant improvements both in terms of design quality and turnaround time compared to manual designs done by experienced designers.
Description Author affiliation: Res. Inst. for Discrete Math., Univ. of Bonn, Bonn, Germany (Hougardy, S.; Nieberg, T.; Schneider, J.)
ISBN 9781467330299
ISSN 21536961
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2013-01-22
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781467330305
Size (in Bytes) 293.10 kB
Page Count 8
Starting Page 453
Ending Page 460

Source: IEEE Xplore Digital Library