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Author Singar, Sumitra ♦ Joshi, N. K. ♦ Ghosh, P. K.
Editor Rossi, Marco
Source Hindawi
Content type Text
Publisher Hindawi
File Format PDF
Copyright Year ©2018
Language English
Abstract Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.
ISSN 16879503
Learning Resource Type Article
Publisher Date 2018-03-29
Rights License This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
e-ISSN 16879511
Journal Journal of Nanotechnology
Volume Number 2018
Page Count 6


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