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Author Chen, Jifeng ♦ Wang, Shuo ♦ Tehranipoor, Mohammad
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2014
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword HCI ♦ NBTI ♦ Reliability analysis ♦ Circuit aging ♦ Path-delay analysis
Abstract Circuit reliability analysis at the presilicon stage has become vital for sub-45nm technology designs in particular, due to aging effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). To avoid potential reliability hazards in the postsilicon stage, current large-scale designs for commercial implementation overpessimistically analyze circuit aging under assumed worst-case workload in order not to violate the corner cases even for low possibilities, thus introducing unnecessary margin in the design timing analysis. The major issue is lack of an effective aging analysis method applicable to large designs with low CPU runtime, which is mainly due to: (1) conventional reliability tools are extremely time-consuming for circuit-level timing analysis and thus are not practical for large designs; (2) mathematical models developed to expedite the process are not accurate due to the high complexity of aging effects. In this article, a comprehensive analysis is presented to highlight the importance of each aging parameter. Then, a novel methodology is developed based on current commercial reliability tools to guarantee its high accuracy on circuit-level aging analysis. Existing proven low-level mathematical models are further enhanced to extensively speed up a higher level analysis by taking advantage of the explicit intermediate conditions stored in a pregenerated lookup table. Our results indicate $≥244\textit{X}$ improved computational efficiency, ≤5% relative error, and ≤0.7% absolute error compared with commercial reliability analysis tools (e.g., HSPICE MOSRA).
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2014-03-06
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 10
Issue Number 2
Page Count 21
Starting Page 1
Ending Page 21

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Source: ACM Digital Library