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Author Jae-sun Seo ♦ Kaul, H. ♦ Krishnamurthy, R. ♦ Sylvester, D. ♦ Blaauw, D.
Sponsorship IEEE Computer Society ♦ Association for Computing Machinery (ACM)/SIGDA ♦ IEEE Computer Society Technical Committee on Design Automation
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1993
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Robustness ♦ Encoding ♦ Energy efficiency ♦ Integrated circuit interconnections ♦ Energy consumption ♦ CMOS technology ♦ Delay ♦ Capacitance ♦ Voltage ♦ Temperature ♦ variation ♦ Bus encoding ♦ interconnects ♦ on-chip communication ♦ repeater
Abstract In this paper, we propose a new circuit technique for on-chip communication, the edge encoding technique, to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2 V 65-nm CMOS technology, the proposed approach achieves up to 34% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 39% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be both larger and more robust to process, voltage, and temperature variations than previous techniques.
Description Author affiliation :: Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA
Author affiliation :: Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
ISSN 10638210
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-02-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 19
Issue Number 2
Size (in Bytes) 1.37 MB
Page Count 10
Starting Page 264
Ending Page 273

Source: IEEE Xplore Digital Library