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Author Sharma, D. K. ♦ Patil, M. B. ♦ Rao, V. R. ♦ Reddy, P. S. ♦ Kumar, D. V. ♦ Narasimhulu, K. ♦ Shojaei-Baghini, M.
Source IIT Bombay
Content type Text
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
File Format HTM / HTML
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Modern physics
Subject Keyword Design ♦ Channel engineering ♦ Look-up table (lut) ♦ Quasi-static ♦ Model ♦ Lateral asymmetric channel (lac) ♦ Profile
Abstract Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-mu m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device.
ISSN 00189383
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-01-01
Journal IEEE Transactions on Electron Devices
Volume Number 52
Issue Number 7
Page Count 7
Starting Page 1603
Ending Page 1609