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Author Pierce, Luke ♦ Tragoudas, Spyros
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2014
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Threshold synthesis ♦ Clocked threshold logic ♦ Design automation ♦ Nanopipeline ♦ Synthesis
Abstract Threshold logic gates allow for complex multiinput functions to be implemented using a single gate thereby reducing the power and area of a circuit. Clocked threshold gates are nanopipelined to increase network throughput. It is shown that synthesis methods that do not consider the synchronization of the nanopipeline can produce an enormous amount of buffers. The proposed algorithm synthesizes a Boolean network into a nanopipelined threshold logic network by minimizing not only the number of combinational clusters but also the associated buffer insertion overhead.
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2014-03-06
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 10
Issue Number 2
Page Count 17
Starting Page 1
Ending Page 17


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Source: ACM Digital Library