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Author Beuchat, Jean-Luc
Source Hyper Articles en Ligne (HAL)
Content type Text
File Format PDF
Language English
Subject Keyword CRYPTOGRAPHY ♦ FPGA ♦ IDEA BLOCK CIPHER ♦ COMPUTER ARITHMETIC ♦ MODULO (2^N+1) MULTIPLICATION ♦ info ♦ Computer Science [cs]/Other [cs.OH]
Abstract The IDEA block cipher is a symmetric-key algorithm which encrypts 64-bit plaintext blocks to 64-bit ciphertext blocks, using a 128-bit secret key. The security of IDEA relies on combining operations from three algebraic groups: integer addition modulo 2^n, bitwise exclusive or of two n-bit words, and integer multiplication modulo (2^n+1) which is the critical arithmetic operation of the block cipher. In this paper, we investigate three algorithms based on a small multiplication with a subsequent modulo correction. They are particularly well suited for the latest FPGA devices embedding small multiplier blocks, like the Virtex-II family. We also consider a multiplier based on modulo (2^n+1) adders. Several architectures of the IDEA block cipher are then described and compared from different point of view: throughput to area ratio or adequation with feedback and non-feedback chaining modes. Our fastest circuit achieves a throughput of 8.5 Gb/s, which is, to our knowledge, the best rate reported in the literature.
Educational Use Research
Learning Resource Type Report ♦ Article
Publisher Date 2002-09-01
Publisher Institution INRIA