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Author Light, R. W. ♦ Bell, H. B.
Source United States Department of Energy Office of Scientific and Technical Information
Content type Text
Language English
Subject Keyword ENGINEERING ♦ MATERIALS SCIENCE ♦ INTEGRATED CIRCUITS ♦ ETCHING ♦ FABRICATION ♦ SILICON ♦ ANISOTROPY ♦ DEPOSITION ♦ EROSION ♦ ISOTROPY ♦ OXYGEN ♦ PHOTORESISTORS ♦ PLASMA ♦ SULFUR DIOXIDE ♦ SULFUR FLUORIDES ♦ TOPOGRAPHY ♦ CHALCOGENIDES ♦ ELECTRICAL EQUIPMENT ♦ ELECTRONIC CIRCUITS ♦ ELEMENTS ♦ EQUIPMENT ♦ FLUORIDES ♦ FLUORINE COMPOUNDS ♦ HALIDES ♦ HALOGEN COMPOUNDS ♦ MICROELECTRONIC CIRCUITS ♦ NONMETALS ♦ OXIDES ♦ OXYGEN COMPOUNDS ♦ RESISTORS ♦ SEMIMETALS ♦ SULFUR COMPOUNDS ♦ SULFUR OXIDES ♦ SURFACE FINISHING ♦ Engineering- Electronic Circuits & Devices- (-1989) ♦ Other Materials- Preparation & Manufacture
Abstract Typical plasma etching techniques used in integrated circuit fabrication can generate steep topographies that cannot be covered adequately by subsequent deposition steps. An SF/sub 6//O/sub 2/ plasma etching process for polysilicon using controlled photoresist erosion produces tapered edge profiles compatible with step coverage requirements. The degree of taper is a function of the photoresist profile, the photoresist to polysilicon etch rate ratio, and the extent of overetch. The photoresist and the polysilicon appear to etch predominantly anisotropically with the isotropic component of the polysilicon etch rate increasing during the overetch period.
Educational Use Research
Learning Resource Type Article
Publisher Date 1983-07-01
Publisher Place United States
Journal J. Electrochem. Soc.
Volume Number 130
Issue Number 7
Organization Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)


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