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Author Hong-Yu Lin ♦ Hsu, S.S.H. ♦ Chih-Yuan Chan ♦ Jun-De Jin ♦ Yu-Syuan Lin
Sponsorship IEEE Circuits and Systems Society
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2004
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Frequency conversion ♦ CMOS technology ♦ Radio frequency ♦ Q factor ♦ Circuits ♦ Energy consumption ♦ Signal processing ♦ TV broadcasting ♦ Frequency estimation ♦ Inductors ♦ divider circuits ♦ Analog circuits ♦ CMOS RF circuits ♦ digital circuits
Abstract A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications.
Description Author affiliation :: Nat. Tsinghua Univ., Hsinchu
ISSN 15497747
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-09-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 54
Issue Number 9
Size (in Bytes) 1.68 MB
Page Count 5
Starting Page 750
Ending Page 754


Source: IEEE Xplore Digital Library