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Author Sai, M.P.D. ♦ Hao Yu ♦ Yang Shang ♦ Chuan Seng Tan ♦ Sung Kyu Lim
Sponsorship IEEE Council on Electronic Design Automation ♦ IEEE Circuits and Systems Society
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1982
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science ♦ Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Through-silicon vias ♦ Stress ♦ Clocks ♦ Delays ♦ Couplings ♦ Integrated circuit modeling ♦ Solid modeling ♦ TSV stress ♦ Clock-skew reduction ♦ electrical-thermal–mechanical coupling ♦ nonlinear MOSCAP ♦ stress gradient ♦ temperature gradient ♦ thermal TSV ♦ through-silicon via (TSV)
Abstract A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The large temperatures and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as a resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model is developed for signal TSVs in 3-D IC. With consideration of liner material and also stress, a nonlinear model is established between electrical delay with temperature and stress. Moreover, sensitivity analysis is performed to relate the reduction of temperature and stress gradients with respect to dummy TSVs insertion. Taking the design of 3-D clock tree as a case study, we have formulated a nonlinear optimization problem for clock-skew reduction. By allocating dummy TSVs to reduce the temperature and stress gradients, the clock skew introduced by signal TSVs and drivers can be minimized. A number of 3-D clock-tree benchmarks are utilized in experiments. We have observed that with the use of dummy TSV insertion, clock skew can be reduced by 61.3% on average when the accurate nonlinear electrical-thermal-mechanical delay model is applied.
Description Author affiliation :: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Author affiliation :: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
ISSN 02780070
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2013-01-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 32
Issue Number 11
Size (in Bytes) 1.01 MB
Page Count 14
Starting Page 1734
Ending Page 1747

Source: IEEE Xplore Digital Library