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Author Miyakawa, Nobuaki ♦ Hashimoto, Eiri ♦ Maebashi, Takanori ♦ Nakamura, Natsuo ♦ Sacho, Yutaka ♦ Nakayama, Shigeto ♦ Toyoda, Shinjiro
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword 3D integration ♦ Design ♦ Hardware ♦ Stacking process
Abstract We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7Ω between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%.
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-11-07
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 4
Issue Number 4
Page Count 15
Starting Page 1
Ending Page 15

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Source: ACM Digital Library