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Author Cheng, Ching-Hwa
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2015
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Power gate ♦ Dynamic power reduction ♦ Power-performance trade-off ♦ Rising voltage
Abstract It has been proposed that small amounts of energy dissipate when transfer through a rising Vdd. In typical power gate circuits, the PMOS transistors $(P_{SW})$ reduce the leakage of power by shutting off outer Vdd to the idle blocks. We expand this technique by utilizing active $P_{SW},$ which are turned on and off by a clock signal. The proposed SCKVdd technique combines the power source gated mechanism and clock signal to generate stable progressive rising voltage to suppress peak and average currents effectively. The SCKVdd technique is a scalable, clock-controlled, self-stabilized voltage technique. This technique is easily implemented in generic digital circuits to reduce power dissipation. A normal CMOS circuit shows a dynamic power consumption increase proportional to the clock frequency. SCKVdd results in a lower-than-usual frequency dependency, and is suitable for high speed clock circuits. SCKVdd can be integrated with frequency, voltage scaling and an activated $P_{SW}$ number to implement an efficient power-performance trade-off mechanism. In experiments that investigated constant Vdd for MPEG VLD chips, power dissipation savings were in the range of 42% to 54% with only a small delay penalty.
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2015-08-03
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 12
Issue Number 1
Page Count 24
Starting Page 1
Ending Page 24


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Source: ACM Digital Library