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Author Wolf, W.
Sponsorship IEEE Education Society
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1963
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Very large scale integration ♦ Logic design ♦ Design methodology ♦ Design automation ♦ Circuit synthesis ♦ Logic circuits ♦ Chip scale packaging ♦ Standards development ♦ Large scale integration ♦ Silicon
Abstract The VLSI project class at Princeton University has been redesigned, using modern logic and layout synthesis tools, to emphasize system design issues. The design methodology taught in the class allows students to build larger designs; it also allows them to learn, by redesign, how to trade off layout, circuit, logic, and architectural design problems. Two synthesis tools were developed (based on the Oct tool set from UC Berkeley) to generate standard cell layouts: one which takes as input finite-state machine transition tables; and one which generates netlists using C programs. The author describes; what is important for students to learn in a VLSI design class; the design methodology developed to teach this curriculum through a design project; and the CAD tools used to support this design methodology.<<ETX>>
Description Author affiliation :: Dept. of Electr. Eng., Princeton Univ., NJ, USA
ISSN 00189359
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1992-02-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 35
Issue Number 1
Size (in Bytes) 616.16 kB
Page Count 7
Starting Page 11
Ending Page 17


Source: IEEE Xplore Digital Library