### Inexact computing using probabilistic circuits: Ultra low-power digital processingInexact computing using probabilistic circuits: Ultra low-power digital processing

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 Author Kim, Jaeyoon ♦ Tiwari, Sandip Source ACM Digital Library Content type Text Publisher Association for Computing Machinery (ACM) File Format PDF Copyright Year ©2014 Language English
 Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science Subject Keyword Energy-efficiency ♦ MSB-LSB weighted supply voltage scaling ♦ Monte Carlo simulations ♦ Probability of calculation error ♦ Reliability ♦ Statistical performance metric ♦ Variations Abstract Numerous computing applications can tolerate low error rates. In such applications, inexact approaches provide the ability to achieve significantly lower power. This work demonstrates the power-error trade-offs that can be achieved. Using probabilistic modeling in sub-50-nm silicon transistor technology, the relationship between statistical uncertainties and errors are elucidated for different configurations and topologies and the trade-offs quantified. Gate-level implementation of the probabilistic CMOS logic is validated by circuit simulations of a commercial 45-nm SOI CMOS process technology. Using a practical ALU architecture where voltages can be scaled from most significant to least significant bit blocks as an example, the potential benefits of this technique are shown. A calculation error of $10^{™6},$ an error rate quite tolerable for many computational tasks, is shown to be possible with a total power reduction of more than 40%. ISSN 15504832 Age Range 18 to 22 years ♦ above 22 year Educational Use Research Education Level UG and PG Learning Resource Type Article Publisher Date 2014-03-06 Publisher Place New York e-ISSN 15504840 Journal ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume Number 10 Issue Number 2 Page Count 23 Starting Page 1 Ending Page 23

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Source: ACM Digital Library