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Author Voyiatzis, I.
Sponsorship IEEE Computer Society Technical Committee on Distributed Process ♦ IEEE Computer Society Technical Committee on VLSI ♦ IEEE Technical Committee on Computer Architecture ♦ IEEE Computer Society
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1968
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Random access memory ♦ Couplings ♦ Built-in self-test ♦ Testing ♦ Logic gates ♦ Algorithm design and analysis ♦ Circuit faults ♦ Memory control and access ♦ Semiconductor Memories ♦ Reliability ♦ Testing and Fault-Tolerance ♦ Test generation ♦ Built-In Tests ♦ Memory control and access ♦ Semiconductor Memories ♦ Reliability ♦ Testing and Fault-Tolerance ♦ Test generation ♦ Built-In Tests
Abstract Testing of word-organized memories has been performed in one of these three ways: (1) by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intraword fault model), (2) by applying special tests to target intraword faults in addition to applying tests for bit-organized memories, or (3) by applying march tests bit-by-bit to the memory words. The latter solution results in decreased hardware overhead. In this paper, a novel Built-in Self-Test (BIST) scheme is proposed to serially apply march tests bit-by-bit to word-organized RAMs, utilizing an ALU whose inputs are driven by a barrel shifter. Comparisons with schemes that have been proposed in the open literature for the same purpose reveal that the proposed scheme achieves the same fault coverage within the same or lower time and with lower area overhead. More precisely, an overhead of n + 3 gates is required for the application of the required patterns to the RAM inputs and the evaluation of the corresponding outputs, as opposed to the 8n or 11n gates required by schemes proposed previously.
Description Author affiliation :: Technol. Educ. Inst. of Athens, Athens
ISSN 00189340
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-05-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 57
Issue Number 5
Size (in Bytes) 4.44 MB
Page Count 14
Starting Page 577
Ending Page 590


Source: IEEE Xplore Digital Library