### Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and MitigationVariability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation

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 Author Narayanan, Pritish ♦ Leuchtenburg, Michael ♦ Kina, Jorge ♦ Joshi, Prachi ♦ Panchapakeshan, Pavan ♦ Chui, Chi On ♦ Moritz, C Andras Source ACM Digital Library Content type Text Publisher Association for Computing Machinery (ACM) File Format PDF Copyright Year ©2013 Language English
 Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science Subject Keyword NASICs ♦ Nanoscale computing fabrics ♦ Built-in fault tolerance ♦ Circuit simulation ♦ Crossed nanowire field effect transistors ♦ Device modeling ♦ Methodology ♦ Nanodevices ♦ Parameter variability ♦ Parameter variation Abstract Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers. A final contribution of the article includes novel techniques to address this impact. The variability framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For variation of $\textit{σ}$ = 10 in key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal. Monte Carlo simulations using an architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. New built-in variation mitigation and fault-tolerance schemes, leveraging redundancy, asymmetric delay paths and biased voting schemes, were developed and evaluated to mitigate these effects. They are shown to improve performance by up to 7.5X on a nanoscale processor design with variation, and improve performance in designs relying on redundancy for defect tolerance, without variation assumed. Techniques show up to 3.8X improvement in effective-yield performance products even at a high 12% defect rate. The suite of techniques provides a design space across key system-level metrics such as performance, yield and area. ISSN 15504832 Age Range 18 to 22 years ♦ above 22 year Educational Use Research Education Level UG and PG Learning Resource Type Article Publisher Date 2013-02-01 Publisher Place New York e-ISSN 15504840 Journal ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume Number 9 Issue Number 1 Page Count 24 Starting Page 1 Ending Page 24

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Source: ACM Digital Library