### ULS: A $dual-V_th$/high-κ nano-CMOS universal level shifter for system-level power managementULS: A $dual-V_th$/high-κ nano-CMOS universal level shifter for system-level power management

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 Author Mohanty, Saraju P. ♦ Pradhan, Dhiraj K. Source ACM Digital Library Content type Text Publisher Association for Computing Machinery (ACM) File Format PDF Copyright Year ©2010 Language English
 Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science Subject Keyword Analog/Mixed-Signal System-on-a-Chip (AMS-SoC) ♦ DC-to-DC voltage-level shifter ♦ Power management ♦ Dual-threshold voltage ♦ High-κ/metal-gate nano-CMOS ♦ Low-power design ♦ Nanoscale CMOS ♦ System-level power management Abstract Power dissipation is a major bottleneck for emerging applications, such as implantable systems, digital cameras, and multimedia processors. Each of these applications is essentially designed as an Analog/Mixed-Signal System-on-a-Chip (AMS-SoC). These AMS-SoCs are typically operated from a single power-supply source which is a battery providing a constant supply voltage. In order to reduce power dissipation of the AMS-SoCs, multiple-supply voltage and/or variable-supply voltage is used as an attractive low-power design approach. In the multiple-/variable-supply voltage AMS-SoCs the use of a DC-to-DC voltage-level shifter is critical. The voltage-level shifter is an overhead when its own power dissipation is high. In this article a new DC-to-DC voltage-level shifter is introduced that performs level-up shifting, level-down shifting, and blocking of voltages and is called Universal Level Shifter (ULS). The ULS is a unique component that reduces dynamic power and leakage of the AMS-SoCs while facilitating their reconfigurability. The system-level architectures for three AMS-SoCs, such as Drug Delivery Nano-Electro-Mechanical-System (DDNEMS), Secure Digital Camera (SDC), and Net-centric Multimedia Processor (NMP) are introduced to demonstrate the use the ULS for system-level power management. The article presents a design flow and an algorithm for optimal design of the ULS using a $dual-V_{th}$ high-κ technique for efficient realization of ULS. A prototype ULS is presented for 32nm nano-CMOS technology node. The robustness of the ULS design is examined by performing three types of analysis, such as parametric, load, and power. It is observed that the ULS produces a stable output for voltages as low as 0.35 V and loads varying from 50 $\textit{fF}$ to 120 $\textit{fF}.$ The average power dissipation of the ULS with a 82 $\textit{fF}$ capacitive load is 5 μ $\textit{W}.$ ISSN 15504832 Age Range 18 to 22 years ♦ above 22 year Educational Use Research Education Level UG and PG Learning Resource Type Article Publisher Date 2008-06-01 Publisher Place New York e-ISSN 15504840 Journal ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume Number 6 Issue Number 2 Page Count 26 Starting Page 1 Ending Page 26

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Source: ACM Digital Library