|Author||Liang, Jiale ♦ Yeh, Stanley ♦ Wong, S Simon ♦ Wong, H-S Philip|
|Source||ACM Digital Library|
|Publisher||Association for Computing Machinery (ACM)|
|Subject Domain (in DDC)||Computer science, information & general works ♦ Data processing & computer science|
|Subject Keyword||Cu wire ♦ Interconnect ♦ Cross-point memory array ♦ Energy consumption ♦ Latency ♦ Read margin ♦ Reliability ♦ Scaling ♦ Write margin|
|Abstract||The impact of wordline/bitline metal wire scaling on the write/read performance, energy consumption, speed, and reliability of the cross-point memory array is quantitatively studied for technology nodes down to single-digit nm. The impending resistivity increase in the Cu wires is found to cause significant decrease of both write and read window margins at the regime when electron surface scattering and grain boundary scattering are substantial. At deeply-scaled device dimensions, the wire energy dissipation and wire latency become comparable to or even exceed the intrinsic values of memory cells. The large current density flowing through the wordlines/bitlines raises additional reliability concerns for the cross-point memory array. All these issues are exacerbated at smaller memory resistance values and larger memory array sizes. They thereby impose strict constraints on the memory device design and preclude the realization of large-scale cross-point memory array with minimum feature sizes beyond the 10 nm node. A rethink in the design methodology of cross-point memory to incorporate and mitigate the scaling effects of wordline/bitline is necessary. Possible solutions include the use of memory wires with better conductivity and scalability, memory arrays with smaller partition sizes, and memory elements with larger resistance values and resistance ratios.|
|Age Range||18 to 22 years ♦ above 22 year|
|Education Level||UG and PG|
|Learning Resource Type||Article|
|Publisher Place||New York|
|Journal||ACM Journal on Emerging Technologies in Computing Systems (JETC)|
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