### Reliability improvement of logic and clock paths in power-efficient designsReliability improvement of logic and clock paths in power-efficient designs

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 Author Arasu, Senthil ♦ Nourani, Mehrdad ♦ Reddy, Vijay ♦ Carulli, John M ♦ Kapila, Gautam ♦ Chen, Min Source ACM Digital Library Content type Text Publisher Association for Computing Machinery (ACM) File Format PDF Copyright Year ©2014 Language English
 Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science Subject Keyword Negative Bias Temperature Instability (NBTI) ♦ Positive Bias Temperature Instability (PBTI) ♦ Clock network design ♦ Clock tree reliability ♦ Logic paths reliability ♦ Signal probability Abstract Performance degradation due to transistor aging is a significant impediment to high-performance IC design due to increasing concerns of reliability mechanisms such as negative-bias-temperature-instability (NBTI). The concern only grows with technology scaling as the effects of positive bias temperature instability (PBTI) is becoming prominent in future technologies and compounding with the effects of NBTI. Although aging of transistor is inevitable and the magnitude of degradation due to aging varies depending upon the context. Specifically, in power-efficient systems designs, the logic and clock paths are susceptible to static stress resulting in peak degradation due to BTI occurrence when clock is gated. In this article, we present the reliability impact of making systems power efficient and propose a design-for-reliability methodology that can be used in conjunction with low-power design techniques to alleviate the stress conditions caused by rendering circuits in idle state. The $technique—\textit{BTI-Refresh},$ is shown to be applicable to both logic and clock paths alike and focuses on preventing prolonged static stress using periodic refreshes to achieve alternating stress. The mechanism is shown to integrate seamlessly into the design at gate-level without requiring any architectural or RT-level changes. Using ISCAS benchmarks and Kogge-Stone-Adder circuits, it is shown to reduce the aging effect in logic path delay due to static stress by up to 50% with negligible area and power overhead. $\textit{BTI-Refresh}$ is extended to clock-paths to prevent pulse-width degradation due to static aging and with minimal clock-skew. ISSN 15504832 Age Range 18 to 22 years ♦ above 22 year Educational Use Research Education Level UG and PG Learning Resource Type Article Publisher Date 2014-01-01 Publisher Place New York e-ISSN 15504840 Journal ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume Number 10 Issue Number 1 Page Count 23 Starting Page 1 Ending Page 23

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Source: ACM Digital Library