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Author Wu, Jigang ♦ Srikanthan, Thambipillai ♦ Wang, Kai
Source SpringerLink
Content type Text
Publisher SP Higher Education Press
File Format PDF
Copyright Year ©2009
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Mesh ♦ reconfiguration ♦ processor array ♦ routing ♦ algorithm ♦ Computer Science
Abstract Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋$^{ th }$) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.
ISSN 16737350
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2009-05-16
Publisher Institution Chinese Universities
Publisher Place Heidelberg
e-ISSN 16737466
Journal Frontiers of Computer Science in China
Volume Number 3
Issue Number 3
Page Count 7
Starting Page 315
Ending Page 321

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Source: SpringerLink