### Spin-transfer torque magnetic random access memory (STT-MRAM)Spin-transfer torque magnetic random access memory (STT-MRAM)

Access Restriction
Subscribed

 Author Apalkov, Dmytro ♦ Khvalkovskiy, Alexey ♦ Watts, Steven ♦ Nikitin, Vladimir ♦ Tang, Xueti ♦ Lottis, Daniel ♦ Moon, Kiseok ♦ Luo, Xiao ♦ Chen, Eugene ♦ Ong, Adrian ♦ Driskill-Smith, Alexander ♦ Krounbi, Mohamad Source ACM Digital Library Content type Text Publisher Association for Computing Machinery (ACM) File Format PDF Copyright Year ©2013 Language English
 Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science Subject Keyword MRAM ♦ Magnetic memory ♦ Magnetic tunneling junction ♦ Spin polarization ♦ Spin transfer torque ♦ Tunneling magnetoresistance Abstract Spin-transfer torque magnetic random access memory (STT-MRAM) is a novel, magnetic memory technology that leverages the base platform established by an existing 100+nm node memory product called MRAM to enable a scalable nonvolatile memory solution for advanced process nodes. STT-MRAM features fast read and write times, small cell sizes of $6F^{2}$ and potentially even smaller, and compatibility with existing DRAM and SRAM architecture with relatively small associated cost added. STT-MRAM is essentially a magnetic multilayer resistive element cell that is fabricated as an additional metal layer on top of conventional CMOS access transistors. In this review we give an overview of the existing STT-MRAM technologies currently in research and development across the world, as well as some specific discussion of results obtained at Grandis and with our foundry partners. We will show that in-plane STT-MRAM technology, particularly the DMTJ design, is a mature technology that meets all conventional requirements for an STT-MRAM cell to be a nonvolatile solution matching DRAM and/or SRAM drive circuitry. Exciting recent developments in perpendicular STT-MRAM also indicate that this type of STT-MRAM technology may reach maturity faster than expected, allowing even smaller cell size and product introduction at smaller nodes. ISSN 15504832 Age Range 18 to 22 years ♦ above 22 year Educational Use Research Education Level UG and PG Learning Resource Type Article Publisher Date 2013-05-01 Publisher Place New York e-ISSN 15504840 Journal ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume Number 9 Issue Number 2 Page Count 35 Starting Page 1 Ending Page 35

#### Open content in new tab

Source: ACM Digital Library