Access Restriction

Author Frachtenberg, Eitan
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Memory Hierarchy ♦ Chip Heterogeneity ♦ Future Architecture ♦ Parallelaware Scheduling ♦ Commodity O Scheduler ♦ Commodity O ♦ Main Issue ♦ O Scheduler ♦ Parallel Desktop ♦ Process Scheduling ♦ Design Principle ♦ Operating System ♦ Chip Parallelism ♦ Scalable Os ♦ Parallel Architecture ♦ Process Scheduling Requirement ♦ New Approach ♦ Software Warrant ♦ Imminent Change ♦ Cant Performance Degradation ♦ Parallel Job ♦ Multicore Chip ♦ Commodity Hardware ♦ Different Domain-speci ♦ New Complexity ♦ Ne-grained Power Management ♦ Parallel Program
Description Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power management, and most importantly, chip parallelism. Similarly, workloads are growing more concurrent and diverse. With this new complexity in hardware and software, process scheduling in the operating system (OS)becomes more challenging. Nevertheless, most commodity OS schedulers are based on design principles that are 30 years old. This disparity may soon lead to signi cant performance degradation. Most signi cantly, parallel architectures such as multicore chips require more than scalable OSs: parallel programs require parallelaware scheduling. This paper posits that imminent changes in hardware and software warrant reevaluating the scheduler's policies in the commodity OS. We discuss and demonstrate the main issues that the emerging parallel desktops are raising for the OS scheduler. We propose that a new approach to scheduling is required, applying and generalizing lessons from different domain-speci c scheduling algorithms, and in particular, parallel job scheduling. Future architectures can also assist the OS by providing better information on process scheduling requirements. 1
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2005-01-01
Publisher Institution in Parallel Architectures,Algorithms and Networks, 2005. ISPAN 2005. Proceedings. 8th International Symposium on