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Author Grass, E. ♦ Jones, S.
Source CiteSeerX
Content type Text
Publisher Society Press
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Data-driven Processing Structure ♦ Clocked Circuit ♦ Different Level ♦ Important Strategy ♦ Circuit Operation Activity ♦ Important Aim ♦ New Bicmos Current-sensing Circuit ♦ Optimal Utilisation ♦ Power Dissipation ♦ Current Research ♦ 4-bit Parallel Multiplier ♦ Many Problem ♦ Addition Self-timed Circuit ♦ Integrated Circuit ♦ Asynchronous Circuit ♦ Current-sensing Completion Detection ♦ Power Consumption ♦ Power Optimal System ♦ Dual Rail ♦ Operating Condition
Description Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC's) which fully support the advantages of CSCD are presented. Multiple localised CSC's are studied and an example of a 4-bit parallel multiplier is investigated on different levels of granularity. 1 Introduction Minimising the power dissipation of integrated circuits is one of the most important aims of current research. Data-driven processing structures, based on asynchronous (CMOS-) circuits allow reduced circuit operation activity and they therefore appear to be an important strategy for designing low-power and power optimal systems. In addition self-timed circuits provide optimal utilisation of the performance under all operating conditions and avoid many problems and constraints which are caused by clocked circuits such as clock-skew an...
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 1995-01-01
Publisher Institution Proc. of the 2nd Working Conference on Asynchronous Design Methodologies, IEEE Computer