|Author||Balakrishnan, Karthik ♦ Vidit, N. ♦ Easwar, Siddharth ♦ Lim, Sung Kyu|
|Subject Domain (in DDC)||Computer science, information & general works ♦ Data processing & computer science|
|Subject Keyword||Compro-mising Total Wirelength ♦ Enhanced Performance Capability ♦ Maximum Temperature Reduction ♦ Layered Technology ♦ Global Placement ♦ Compact Nature ♦ Maximum Temperature ♦ Dynamic Power Consumption Reduction ♦ Global Routing ♦ Global Wire Congestion ♦ Smooth Tradeoff ♦ Local Wire Congestion ♦ Thermal Issue ♦ Modied Gain Function ♦ Wire Congestion ♦ Experimental Result ♦ Multi-level Min-cut Placement ♦ Full-length Thermal Analysis ♦ Reduced Wire-length|
|Description||from its enhanced performance capabilities and reduced wire-length. However, wire congestion and thermal issues are exacer-bated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce the maximum temperature and wire congestion of 3D circuits without compro-mising total wirelength and via count. Our approach consists of two phases. First, we use a multi-level min-cut placement with a modied gain function for local wire congestion and dynamic power consumption reduction. Second, we perform simulated annealing together with full-length thermal analysis and global routing for global wire congestion and maximum temperature reduction. Our experimental results show smooth tradeoff among congestion, temperature, wirelength, and via. I.
in Proc. Conf. Asia South Pacific Des. Autom
|Educational Role||Student ♦ Teacher|
|Age Range||above 22 year|
|Education Level||UG and PG ♦ Career/Technical Study|
|Learning Resource Type||Article|
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