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Author Shelar, Rupesh S. ♦ Wang, Xinning
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Benchmark Circuit ♦ Conventional Technology ♦ Congestion Map ♦ Nm Technology Show ♦ Vlsi Design ♦ Matching Phase ♦ Dynamic Programming Framework ♦ Probabilistic Congestion Map ♦ Delay Constraint ♦ Experimental Result ♦ Efficient Technology ♦ Serious Concern ♦ Track Overflow
Description in Proc. ISPD
Routing congestion has become a serious concern in today’s VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delayoptimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2005-01-01