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Author Yuan, Feng ♦ Xu, Qiang
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Psn Effect ♦ Capture Phase ♦ Modular System-on-a-chip ♦ Core Test ♦ Excessive Power Supply Noise ♦ Scan-tested Core ♦ Soc Test Architecture Design ♦ Psn-aware Test Generation Technique ♦ Intercore Psn Effect ♦ Unnecessary Yield Loss ♦ Good Chip ♦ Optimization Process ♦ Soc Power Distribution Network ♦ Experimental Result ♦ Novel Design ♦ Power Supply Noise Effect ♦ Fast Inter-core Psn Estimation Method ♦ Core Provider ♦ Soc Test Controller ♦ Manufacturing Test ♦ Time Penalty
Description Excessive power supply noise (PSN) during testing can erroneously cause good chips to fail the manufacturing test, thus leading to unnecessary yield loss. While there are some emerging methodologies such as PSN-aware test generation technique to tackle this problem, they are not readily applicable in modular system-on-a-chip (SoC) testing. This is because: (i). embedded core tests are usually prepared by core providers who are not knowledgeable about the SoC power distribution network; (ii) embedded cores are usually tested in parallel to reduce testing time, but the associated intercore PSN effects are not considered in existing SoC test architecture design and optimization process. In this paper, we present a fast inter-core PSN estimation method and use it to guide the test scheduling process to solve the PSN-induced SoC test yield loss problem. In addition, upon observing that the PSN effects usually manifest themselves only during the capture phase for scan-tested cores, we introduce novel design for test (DfT) structures into SoC test controller to avoid PSN effects with negligible testing time penalty. Experimental results demonstrate the effectiveness of the proposed solution. 1
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2008-01-01
Publisher Institution In Proceedings IEEE International Test Conference (ITC), paper 26.2