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Author Carlsson, Jonas ♦ Palmkvist, Kent ♦ Wanhammar, Lars
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword 2-d Dct Processor ♦ Port Controller Gal Implementation ♦ Port Controller ♦ Design Efficiency ♦ Globally Asynchronous Locally Synchronous ♦ 2-dimensional Dct Processor ♦ Design Effort ♦ Divide-and-conquer Approach ♦ Us Standard Cell ♦ Gal Approach
Abstract Abstract: This paper describes an implementation of a 2-dimensional DCT processor and shows that the Globally Asynchronous Locally Synchronous (GALS) approach is highly suitable for implementation of such processors. Primarily the GALS approach increases the design efficiency by supporting the divide-and-conquer approach. The port controllers described uses standard cells to minimize the design effort when migrating between CMOS processes. The port controllers has been tested in an FPGA. 1.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article