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Author Suh, Jinwoo ♦ Ung, Monte ♦ Prasanna, Viktor K.
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Description this paper, we show high throughput implementation of SAR on High Performance Computing (HPC) platforms. In our implementation, the processors are divided into two groups of size M and N . The first group consisting of M processors computes the FDC (Frequency Domain Convolution) in range dimension, and the second group of N processors computes the FDC in azimuth dimension.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 1997-01-01
Publisher Institution in proceedings of the IEEE International Conference on Algorithms And Architectures for Parallel Processing