Thumbnail
Access Restriction
Open

Author Ker, Ming-Dou ♦ Chen, Wen-Yi
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Over-gate-driven Effect ♦ Esd Protection Circuit ♦ Deep-submicron Cmos Process ♦ New Design ♦ Esd Robustness ♦ Significant Improvement ♦ Different Cmos ♦ Nmos Device ♦ Process Step ♦ Deep-submicron Cmos Ic ♦ Gate-driven Technique ♦ Mask Layer ♦ Experimental Result ♦ Esd Level ♦ Maximum Esd Capability ♦ Circuit Design
Abstract Although the gate-driven (or gate-coupled) technique was reported to improve ESD robustness of NMOS devices, the over-gate-driven effect has been found to degrade ESD level. This effect makes the gate-driven technique hard to be well optimized in deep-submicron CMOS ICs. In this work, a new design is proposed to overcome such over-gate-driven effect by circuit design and to achieve the maximum ESD capability of devices. The experimental results have shown significant improvement on the machine-model (MM) ESD robustness of ESD protection circuit by this new proposed design. This new design is portable (process-migration) for applications in different CMOS processes without modifying the process step or mask layer.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study