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Author Gschwind, Michael ♦ Hofstee, Peter ♦ Flachs, Brian ♦ Hopkins, Martin ♦ Watanabe, Yukio ♦ Yamazaki, Takeshi
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Multicore Architecture ♦ Synergistic Processing ♦ Spu Architecture Implement Novel
Abstract EIGHT SYNERGISTIC PROCESSOR UNITS ENABLE THE CELL BROADBAND ENGINE S BREAKTHROUGH PERFORMANCE. THE SPU ARCHITECTURE IMPLEMENTS A NOVEL, PERVASIVELY DATA-PARALLEL ARCHITECTURE COMBINING SCALAR AND SIMD PROCESSING ON A WIDE DATA PATH. A LARGE NUMBER OF SPUS PER CHIP PROVIDE HIGH THREAD-LEVEL PARALLELISM.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Publisher Date 2006-01-01