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Author Ghaida, Rani S. ♦ Gupta, Puneet
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Overlay Budget Requirement ♦ Overlay Electrical Impact ♦ Design-overlay Interaction ♦ Average Capacitance Variation ♦ Design Parameter ♦ Layer Translates ♦ Different Overlay Source ♦ Wire Spreading ♦ Electrical Impact ♦ Overlay Sampling ♦ Alignment Strategy ♦ Cd Variability ♦ Electrical Impact Reduces ♦ Tough Challenge ♦ Large Effect ♦ Negligible Electrical Impact ♦ Overlay Error ♦ Horizontal Metallization ♦ Beol Dpl ♦ Translation Overlay ♦ Relative Effect ♦ Positive-tone Dpl ♦ Overlay Source ♦ Metal Double Patterning ♦ Cd Uniformity Budget ♦ Overlay Control ♦ Experimental Result ♦ Double Patterning Lithography ♦ Capacitance Variation
Description In double patterning lithography (DPL), overlay error between two patterning steps at the same layer translates into CD variability. Since CD uniformity budget is very tight, overlay control becomes a tough challenge for DPL. In this paper, we electrically evaluate overlay error for BEOL DPL with the goal of studying relative effects of different overlay sources and interactions of overlay control with design parameters. Experimental results show the following: (a) overlay electrical impact is not significant in case of positive-tone DPL (< 3.4 % average capacitance variation) and should be the base for determining overlay budget requirement; (b) when considering congestion, overlay electrical impact reduces in positive-tone DPL; (c) Design For Manufacturability (DFM) techniques like wire spreading can have a large effect on overlay electrical impact (20 % increase of spacing can reduce capacitance variation by 22%); (d) translation overlay has the largest electrical impact compared to other overlay sources; and (e) overlay in y direction (x for horizontal metallization) has negligible electrical impact and, therefore, preferred routing direction should be taken into account for overlay sampling and alignment strategies.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2009-01-01
Publisher Institution Proc. SPIE Design Manufacturability Through DesignProcess Integr