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Author Mishchenko, Alan ♦ Een, Niklas ♦ Brayton, Robert ♦ Chauhan, Pankaj ♦ Sharma, Nikhil
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Semi-canonical Form ♦ Sequential Aigs ♦ Eda Tool ♦ Design Suite ♦ Sequential Circuit ♦ Semi-canonical Labeling ♦ Computed Result ♦ Sequential Aig ♦ Substantial Structural Similarity ♦ Numerous Eda Flow ♦ Time-consuming Computation ♦ Isomorphic Component
Abstract In numerous EDA flows, time-consuming computations are repeatedly applied to sequential circuits. This motivates developing methods to determine what circuits have been processed already by a tool. This paper proposes an algorithm for semi-canonical labeling of nodes in a sequential AIG, allowing problems or sub-problems solved by an EDA tool to be cached with their computed results. This can speed up the tool when applied to designs with isomorphic components or design suites exhibiting substantial structural similarity. 1.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article