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Author Shriraman, Arrvindh ♦ Dwarkadas, Hya ♦ Scott, Michael L.
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Big Instruction ♦ Superscalar Execution ♦ Future Isas Need ♦ Instruction-level Parallelism ♦ Inherent Concurrency Information ♦ Low-level Operation ♦ Application Sequential Thread ♦ Program-level Intent ♦ Traditional Cisc Philosophy ♦ Today Machine ♦ Available Ilp ♦ Large Number ♦ Concurrent Execution ♦ Theoretical Limit ♦ Extra Work ♦ Many Design Choice ♦ Data Flow ♦ Ilp Inherent ♦ Modern Twist ♦ Specific Algorithm
Abstract Instruction-level parallelism (ILP) typically refers to the concurrent execution of instructions (as defined in the instruction set architecture (ISA)) in an application’s sequential thread of execution. There are many design choices in both software (e.g., choice of algorithm) and hardware (e.g., pipelining, superscalar execution) that control the degree of independence and thus the available ILP in today’s machines. Given a specific algorithm, however, the ability to expose the theoretical limits of ILP inherent in the algorithm clearly depends on the types of instructions in the ISA. Our premise is that future ISAs need to return to the traditional CISC philosophy with a modern twist—specifically, using encodings that convey more program-level intent to hardware, including data flow and inherent concurrency—information that hardware would otherwise require extra work to extract. Such “big instructions ” can encode the relationships among large numbers of low-level operations. They
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study