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Author Nyathi, Jabulani ♦ Beiu, Valeriu ♦ Tatapudi, Suryanarayana ♦ Betowski, David
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Noise Suppression Logic ♦ Noise Immune ♦ Differential Noise-immune Threshold Logic ♦ Section Ii ♦ Enhanced Performance ♦ Noise Differential Noise-immune Perceptron ♦ Differential Logic ♦ Suppression Logic Block ♦ Solit-level Orecharge Differential Loeic ♦ Many Different Tlg ♦ Extensive Simulation ♦ Index Terms-charge Recycling ♦ Abslmct-this Paper ♦ Section Iii ♦ Noise-immune Differential Charge ♦ Concluding Remark ♦ Differential Noise Immune Perceptron ♦ Nano Device ♦ Cm-ntl Gate ♦ Improved Noise Immunity ♦ Split-level Precharge Differential Tlgs ♦ Charge Implementation ♦ Noise Immunity Implementation ♦ Logic Bank ♦ New Gate ♦ Pm Cmos Technology ♦ Threshold Logic Gate
Description Abslmct-This paper proposes a new differential neural These emerging nano devices have led to many different TLG inspired gate with improved noise immunity. The charge implementations such as those presented in [SI, [91, [lo]. recycling differential noise-immune threshold logic (CRD-NTL) In this paper we shall focus primarily on charge recycling perceptron is based on combining the split-level precharge differential TLGs, with Section II providing a review of some differential logic, with a technique for enhancing noise immunity implementations of these gates, Section III focusing on a new of threshold logic gates: noise suppression logic. Another idea included in the design of the Cm-NTL gate is the use of two noise-immune differential charge recycling PerCeptrOn and threshold logic banks implementing the function a and its some concluding remarks in Section N. The charge recycling inverse (f-bar), and working in conjunction with the noise differential noise-immune perceptron is based on combining suppression logic blocks for enhanced Performance. the solit-level orecharge differential loeic (SPDL) II 11. with a Characterization of the new gate has been perford by extensive simulation in 0.25 pm CMOS technology at 2.5 V. Index Terms-Charge recycling, differential, noise immune,
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2004-01-01
Publisher Institution Proc. Intl. Joint Conf. Neural Networks