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Author Li, Cheng-Hong ♦ Carloni, Luca P.
Source CiteSeerX
Content type Text
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Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Block-based Design ♦ Increase Global Performance ♦ Local Intracore Information ♦ Logic Synthesis ♦ Generic Shell Template ♦ Latency Variation ♦ Unnecessary Local Stalling ♦ Synthesized Logic Block ♦ 90-nm Industrial Standard Cell Library ♦ Performance Benefit ♦ Internal Logic Structure ♦ Intracore Logic Design ♦ Sequential Logic Optimization ♦ Limited Design Overhead ♦ System-level Protocol ♦ Downlink Core ♦ Overall System-level Performance ♦ New Valid Data ♦ Output Channel ♦ Semicustom Design ♦ Intercore Communication Channel ♦ Latency-insensitive Design ♦ Data Production ♦ Ultrawideband Baseband Transmitter ♦ Input Channel ♦ Index Term Finite State Machine ♦ Fic-shell Instance ♦ Comprehensive Experimental Analysis ♦ System-level Design ♦ Abstract Latency-insensitive Design ♦ Novel Circuit Design ♦ Intellectual Property Core ♦ Functional Independence Condition ♦ Intracore Logic
Abstract Abstract—Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels. We study how knowledge about the internal logic structure of a core can be applied to the design of its shell to improve the overall system-level performance by avoiding unnecessary local stalling. We introduce the notion of functional independence condition (FIC) and present a novel circuit design of a generic shell template that can leverage FIC. We propose a procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the intracore logic and does not require any input from the designers. Finally, we present a comprehensive experimental analysis that shows the performance benefits and limited design overhead of the proposed technique. This includes the semicustom design of an SoC, an ultrawideband baseband transmitter, using a 90-nm industrial standard cell library. Index Terms—Finite state machines (FSMs), latency-insensitive design (LID), logic synthesis, sequential logic optimization, system-level design, system-on-chip (SoCs). I.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study