|Author||Carter, Jonathan R.|
|Subject Domain (in DDC)||Computer science, information & general works ♦ Data processing & computer science|
|Subject Keyword||Gate Ox ♦ Circuit-level Modeling ♦ Obd Defect ♦ Gate Level ♦ Test Pattern ♦ Neces-sary Input Condition ♦ Traditional Pattern Generator ♦ Operational Obd Defect ♦ Oxide Breakdown ♦ System Level ♦ Device Size ♦ Current Density Increase ♦ Device Failure ♦ Traditional Atpg ♦ Physical Phenomenon ♦ Nand Gate ♦ Combinational Circuit ♦ Detect Error|
|Abstract||As device sizes shrink and current densities increase, the probability of device failures due to gate oxide breakdown (OBD) also increases. To provide designs that are tolerant to such failures, we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level. In this paper, we develop a model for operational OBD defects, and we explore how to test for faults due to OBD. For a NAND gate, we derive the neces-sary input conditions that excite and detect errors due to OBD defects at the gate level. We show that traditional pattern generators fail to exercise all of these defects. Finally, we show that these test patterns can be propa-gated and justified for a combinational circuit in a manner similar to traditional ATPG. 1|
|Educational Role||Student ♦ Teacher|
|Age Range||above 22 year|
|Education Level||UG and PG ♦ Career/Technical Study|
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