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Author Krieger, Rolf ♦ Becker, Bernd ♦ Keim, Martin
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Ordered Binary Decision Diagram ♦ Unknown Initial State ♦ Fault Simulation Procedure ♦ Well-known Fault Simulation ♦ Fault Coverage ♦ Numerous Attempt ♦ Time-consuming Task ♦ Automatic Test Pattern Generator ♦ Sequential Logic ♦ Fault Simulation ♦ Major Cause ♦ Sequential Circuit ♦ Initial State ♦ Synchronous Sequential Circuit ♦ Symbolic Fault Simulation ♦ Multiple Observation Time Test Strategy ♦ Three-valued Logic
Description Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information about the initial state of the circuit. In this case an unknown initial state is assumed which is usually handled by introducing a three-valued logic. As it is well-known fault simulation based on this logic only determines a lower bound of the fault coverage. Recently it has been shown that fault simulation based on the multiple observation time test strategy can improve the accuracy of the fault coverage. In this paper we describe how this strategy can be successfully implemented based on Ordered Binary Decision Diagrams. Our experiments demonstrate the efficiency of the fault simulation procedure developed. I. Introduction Despite numerous attempts to create automatic test pattern generators capable of testing sequential logic this problem remains inherently intractable if a three-valued logic is used. The major cause of the difficulty...
In Design Automation Conf
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 1995-01-01