|Author||Monteiro, José ♦ Devadas, Srinivas ♦ Ashar, Pranav ♦ Mauskar, Ashutosh|
|Subject Domain (in DDC)||Computer science, information & general works ♦ Data processing & computer science|
|Subject Keyword||Behavioral Synthesis ♦ Clock Cycle ♦ Power Management Technique ♦ Power Management ♦ Switching Activity ♦ Identify Condition ♦ Scheduling Technique ♦ Algorithm First Schedule Operation ♦ Throughput Constraint ♦ Execution Unit ♦ Power Dissipation ♦ Shut-down Period ♦ Logic Circuit ♦ Shut-down Technique ♦ Scheduling Algorithm ♦ Present Result|
|Description||“Shut-down ” techniques are effective in reducing the power dissipation of logic circuits. Recently, methods have been developed that identify conditions under which the output of a module in a logic circuit is not used for a given clock cycle. When these conditions are met, input latches for that module are disabled, thus eliminating any switching activity and power dissipation. In this paper, we introduce these power management techniques in behavioral synthesis. We present a scheduling algorithm which maximizes the “shut-down ” period of execution units in a system. Given a throughput constraint and the number of execution units available, the algorithm first schedules operations that generate controlling signals and activates only those modules whose result is eventually used. We present results which show that this scheduling technique can save up to 40 % in power dissipation. I.
in Proceedings of the Design Automation Conference
|Educational Role||Student ♦ Teacher|
|Age Range||above 22 year|
|Education Level||UG and PG ♦ Career/Technical Study|
|Learning Resource Type||Article|
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